1. Field of the Invention
The present invention relates to a memory access apparatus that accesses a memory by direct memory access (DMA) method.
2. Description of the Related Art
Technologies for increasing the performance efficiency of computer systems are advancing at a rapid pace. For example, the demand for efficient data transfer between one memory to another in a computer system or between memory and an input/output (I/O) device is met through such advancing technology.
One such technology for efficient data transfer involves a direct memory access method. In the direct memory access method, instead of the MPU carrying out the data transfer within the computer system, a dedicated data transfer hardware, such as a DMA circuit carries out the data transfer based on the instruction from the MPU (see Japanese Patent Laid-Open Publication No. 2005-275538).
FIG. 8 is a functional configuration of a conventional disk array apparatus 1. The disk array apparatus 1 is an example of a computer system provided with a DMA control circuit which implements direct memory access. The disk array apparatus 1 is connected to host computers 2A and 2B by fiber channel links 3A and 3B, respectively.
The disk array apparatus 1 is a device such as a personal computer that searches for data stored in the disk array apparatus 1 itself, based on instruction data from the host computers 2A and 2B, and makes the found data available to the host computers 2A and 2B.
The disk array apparatus 1 is equipped with a Redundant Arrays of Independent (Inexpensive) Disks (RAID) function, which enables it to read a large volume of data at high speed by combining a plurality of disks 9A and 9B.
The disk array apparatus 1 includes channel adapters 4A and 4B, cache memories 5A and 5B, cache controllers 6A and 6B, disk adapters 7A and 7B, switches 8A and 8B, and the disks 9A and 9B. The functions of the channel adapter 4A, the cache memory 5A, the cache controller 6A, the disk adapter 7A, the switch 8A, and the disk 9A are described next. The functions of the channel adapter 4B, the cache memory 5B, the cache controller 6B, the disk adapter 7B, the switch 8B, and the disk 9B are identical to those of the channel adapter 4A, the cache memory 5A, the cache controller 6A, the disk adapter 7A, the switch 8A, and the disk 9A, respectively.
The channel adapter 4A has a communication interface (I/F) function and carries out data exchange between the disk array apparatus 1 and the host computer 2A. The channel adapter 4A includes a DMA chip that performs data transfer by direct memory access.
The cache memory 5A temporarily stores therein the data written by the host computer 2A to the disk 9A, which incidentally contains a plurality of pieces of data, or the data read by the host computer 2A. The cache controller 6A controls the cache memory 5A. The disk adapter 7A includes a communication interface that carries out data exchange between the disk array apparatus 1 and the disk 9A.
The switch 8A connects the plurality of disks included in the disk 9A, and switches the connection between the disks of the disk 9A and the disk adapter 7A. The disk 9A is controlled by a not shown disk drive. The disk 9A stores therein a plurality of pieces of forwardable (searchable) data.
Upon receiving a read data request from the host computer 2A, the channel adapter 4A checks the cache controller 6A to determine whether the cache memory 5A has the designated data specified by the host computer 2A.
If the cache memory 5A has the specified data, the cache controller 6A notifies the channel adapter 4A that the requested data can be read. The channel adapter 4A reads the relevant data from the cache memory 5A and forwards the data to the host computer 2A.
If the cache memory 5A does not have the specified data, the cache controller 6A reads the data from the disk 9A containing the data requested by the host computer 2A via the disk adapter 7A and the switch 8A, and stores the read data in the cache memory 5A. This is termed as staging.
The cache controller 6A then notifies the channel adapter 4A that the data can be read, whereupon the channel adapter 4A reads the data from the cache memory 5A and forwards the data to the host computer 2A.
Thus, provision of the cache memory 5A in the disk array apparatus 1 shortens the time required by the channel adapter 4A for accessing the data.
Though two host computers are presented here by way of example, the number of host computers can be one, or three or more.
FIG. 9 is a detailed functional configuration of the channel adapter 4A. The channel adapter 4A includes a memory 10, a micro processing unit (MPU) 11, a chip set 12, a protocol chip 13, optical-electrical conversion modules 14A and 14B, and a DMA chip 15.
The protocol chip 13 is a large scale integration (LSI) that controls the protocol of the fiber channel (the fiber channel link 3A) required for connecting to the host computer 2A. A connection between the disk array apparatus 1 and the host computer 2A is established by connecting the protocol chip 13 with the host computer 2A by an optical cable, and the like.
The MPU 11 is a processor that performs the overall control of the channel adapter 4A. The chip set 12 is a memory interface that connects the channel adapter 4A to the memory 10.
The memory 10 is composed of dynamic random access memory (DRAM), etc., and stores therein descriptors (instructions issued by the MPU 11 to the DMA chip 15) created by the MPU 11, search data forwarded by the host computer 2A, etc.
The DMA chip 15 is equipped with a DMA function (that is, includes a DMA circuit) for communicating with the cache memory 5A. The DMA chip 15 carries out communication with the cache memory 5A according to the instruction issued by the MPU 11. In other words, the DMA chip 15 forwards data based on the descriptor created by the MPU 11 and stored in the memory 10.
The MPU 11, the chip set 12, the protocol chip 13, and the DMA chip 15 are interconnected by a Peripheral Component Interconnect (PCI) bus via which data are exchanged. The instruction from the MPU 11 is issued to the protocol chip 13 and the DMA chip 15 via the PCI bus.
Upon receiving the search data from the host computer 2A via the fiber channel link 3A, the channel adapter 4A stores the received search data in the memory 10. The MPU 11 creates a designated descriptor and stores the descriptor in the memory 10.
The DMA chip 15 sequentially reads the descriptors from the memory 10, and compares the search data stored in the memory 10 and the search data stored in the cache memory 5A (a count field and a key field of a record described later). In other words, the DMA chip 15 reads the search data from the memory 10 and the cache memory 5A and compares the two search data.
FIG. 10 is a detailed functional configuration of the DMA chip 15. The DMA chip 15 includes a memory I/F unit 20, a search data reading unit 21, a descriptor controller 23, a key/count reading unit 24, and a cache I/F unit 25.
The memory I/F unit 20 includes a communication interface that connects the DMA chip 15 and the memory 10, and controls the protocol of the communication interface. The memory I/F unit 20 receives the designated data from the memory 10 by controlling the communication interface (that is, by forwarding a request to the communication interface).
The cache I/F unit 25 includes a communication interface that connects the DMA chip 15 and the cache memory 5A, and controls the protocol of the communication interface. The cache I/F unit 25 receives the designated data from the cache memory 5A by controlling the communication interface.
The communication interfaces of the memory I/F unit 20 and the cache I/F unit 25 are PCI buses and each consists of a PCI bus protocol control circuit.
The descriptor controller 23 receives the instruction from the MPU 11 (that is, receives the instruction data), and sequentially reads the descriptors stored in the memory 10.
The descriptor controller 23 extracts information such as address, data length, etc., from the descriptor read from the memory 10 and forwards the extracted information to the search data reading unit 21 and the key/count reading unit 24. The address data includes the address of the data in the cache memory 5A and the memory 10.
The search data reading unit 21 reads the search data of a comparable data length from the memory 10, based on the memory address specified in the descriptor. The search data reading unit 21 includes a buffer 22. The buffer 22 holds (stores) the search data read from the memory 10. The search data stored in the buffer 22 is read by the key/count reading unit 24.
The key/count reading unit 24 reads as the search data the data of the key field or the count field containing data of a comparable length from the cache memory 5A, based on the cache address specified in the descriptor.
Upon receiving the data (search data) from the cache memory 5A via the cache I/F unit 25, the key/count reading unit 24 reads the search data from the buffer 22 of the search data reading unit 21.
Further, the key/count reading unit 24 compares the search data from the cache memory 5A and the search data from the search data reading unit, determines whether the comparison result satisfies the comparison condition (hit) or not (miss), and notifies the determination result to the descriptor controller 23.
The descriptor controller 23, the search data reading unit 21, and the key-count reading unit 24 are each equipped with a control function. Each of the controllers includes a state machine and controls the overall functioning of the DMA while communicating with each other.
FIG. 11 is a schematic for explaining data format of the disk 9A. In Main Frame, the storage area of the disk 9A is demarcated by a plurality of concentric tracks. Data is stored in the form of records on each of the tracks.
Each record has a Count-Key-Data (CKD) format. That is, each record has a count field (C), a key field (K), and a data field (D). The count field has a fixed length, and the key field and the data field have variable lengths.
The count field is header data that indicates the start of the record. The count field holds data length of key field or data field, and End of Track (EOT) data if the record is the last record on the track. Specifically, the count field includes record structure data, key length, data length, and security data.
Record structure data is data that indicates whether a record is the last record on a track. Key length and data length indicate the data length of the key field and the data field, respectively. Security data is tag data that includes a check mark required for error detection using Cyclical Redundancy Check (CRC) and a location data of Block ID (BID) logical volume.
The key field contains attribute data (index, etc.) of the records, used by the Operating System (OS) for distinguishing the records. The data field contains user data.
The channel adapter 4A reads the data stored in the disks 9A and 9B according to the instruction from the host computer 2A, and performs search or writes data to the disks 9A and 9B.
For example, one of the instructions from the host computer 2A can be a key search instruction or an EOT search instruction. A key search instruction is an instruction issued by the host computer 2A to compare the data in the specified key field (hereinafter, “key data”) and the key data stored in the disks 9A and 9B. An EOT search instruction is an instruction issued by the host computer 2A to read the count field of all the records on a track and find the count field containing the EOT data.
Upon receiving a keys search instruction or an EOT search instruction from the host computer 2A, the channel adapter 4A has to perform the action of reading the plurality of records on a track in a looped manner.
FIG. 12 is a sequence diagram of the process procedure of a conventional key search process. It is assumed here that when the host computer 2A issues the key search instruction, all the records on the track to be searched are already stored in the cache memory 5A.
Upon receiving from the host computer 2A the operation parameter specification for performing a key search (1), the MPU 11 of the channel adapter 4A performs a cache hit confirmation process to confirm whether all the records on the track to be searched are already stored in the cache memory 5A (2).
As all the records are assumed to be already stored in the cache memory 5A in this case, the MPU 11 forwards a cache hit notification to the host computer 2A (3). Upon receiving the cache hit notification, the host computer 2A forwards to the MPU 11 a key search instruction, including in it the key data to be searched (4).
The MPU 11 then builds a descriptor to instruct the DMA chip 15 of the channel adapter 4A to read the data in the count fields (hereinafter, “count data”) stored in the cache memory 5A (5). The MPU 11 then instructs the DMA chip 15 to read the count data (6).
The DMA chip 15 reads the count data stored in the cache memory 5A and forwards the read count data to the MPU 11 (7). Based on the key length data included in the count data the MPU 11 performs count analysis to calculate the address of the key field.
Based on the calculated address data, the MPU 11 builds a descriptor to instruct the DMA chip 15 to read the key data stored in the cache memory 5A (9).
The MPU 11 repeats the count analysis process (8) and the descriptor building process (9) required for performing key search until the EOT data is detected in the count data. When the EOT data is detected, the MPU 11 instructs the DMA chip 15 to read the key data (10).
The DMA chip 15 then reads the descriptor built by the MPU 11 (11). Then, based on the address data specified in the descriptor, the DMA chip 15 reads the key data stored in the cache memory 5A, and compares the read key data and the key data specified by the host computer 2A to determine whether the designated comparison condition is satisfied (12).
The DMA chip 15 continues the processes of reading the descriptor (11) and the key data (12) until the comparison condition is satisfied. When the comparison condition is met, the DMA chip 15 forwards a search completion notification to the MPU 11 (13).
Upon receiving the search completion notification, the MPU 11 reads the key search result from the DMA chip 15 and, as a response to the key search instruction (4), notifies the key search result to the host computer 2A (15). Thus, the MPU 11 and the DMA chip 15 divide the key search process between themselves.
However, in the conventional method, the MPU 11 is burdened heavily because of having to create the descriptors for reading the count data and the key data from the cache memory 5A and analyze the count data for calculating the address of the key data in the cache memory 5A.
In other words, once the key search process begins, the load on the MPU 11 increases due to which it is not available for other processes. Therefore, development of a technology is sought which reduces the load on the MPU 11 and allows it to perform other processes even when key search process is underway, thus increasing the performance efficiency of the MPU 11.